1. Field of the Invention
The present invention relates generally to stereolithography and, more specifically, to the use of stereolithography in forming multilayer structures with vertical or near-vertical sides, such structures including packages for semiconductor devices and the like. Most particularly, the present invention relates to forming multilayer structures with sides of enhanced smoothness.
2. State of the Art
In the past decade, a manufacturing technique termed xe2x80x9cstereolithography,xe2x80x9d also known as xe2x80x9clayered manufacturing,xe2x80x9d has evolved to a degree where it is employed in many industries.
Essentially, stereolithography as conventionally practiced, involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually being effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or xe2x80x9cslicedxe2x80x9d into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object, and surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries, followed by selective consolidation or fixation of the material to at least a semisolid state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed, material also at that time being substantially concurrently bonded to a lower layer. The unconsolidated material employed to build an object may be supplied in particulate or liquid form, and the material itself may be consolidated or fixed, or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size, whereas when a liquid is employed, surface resolution is highly dependent upon the minimum surface area of the liquid which can be fixed and the minimum thickness of a layer which can be generated. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end, and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by inkjet printing techniques), or irradiation using heat or specific wavelength ranges.
An early application of stereolithography was to enable rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed might be rapidly generated. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production.
In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques.
To the inventors"" knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products including other, pre-existing components in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results is required. Furthermore, conventional stereolithography apparatus and methods fail to address the difficulties of precisely locating and orienting a number of pre-existing components for stereolithographic application of material thereto without the use of mechanical alignment techniques or to otherwise assuring precise, repeatable placement of components.
In the electronics industry, state-of-the-art packaging of semiconductor dice is an extremely capital-intensive proposition. In many cases, discrete semiconductor dice carried on, and electrically connected to, leadframes are individually packaged with a filled polymer material in a transfer molding process. A transfer molding apparatus is extremely expensive, costing at least hundreds of thousands of dollars in addition to the multi-hundred thousand dollar cost of the actual transfer molding dies in which strips of leadframes bearing semiconductor dice are disposed for encapsulation.
Encapsulative packaging of a semiconductor device already mounted on a substrate by molding and other presently used methods may be very difficult, time-consuming and costly. In some cases, the device may be packaged using a so-called xe2x80x9cglob-topxe2x80x9d material such as a silicone gel, but the package boundaries are imprecisely defined, a dam structure may be required to contain the slumping gel material, and the seal achieved is generally nonhermetic.
The present invention includes a method of forming a precisely dimensioned structure from a photopolymer material by a stereolithographic process. The structure is formed by creating one or more layers of at least partially polymerized material adjacent a preformed electronic component or other small component with a high degree of precision to create a wall adjacent thereto or, optionally, an encapsulative package therefor. For example, a semiconductor die may be provided with a protective structure in the form of a layer of dielectric material having a controlled thickness or depth over or adjacent one or more surfaces thereof. As used herein, the term xe2x80x9cpackagexe2x80x9d as employed with reference to electrical components includes partial, as well as full, covering or encapsulation of a given semiconductor die surface with a dielectric material, and specifically includes fabrication of a semiconductor die configured in a so-called xe2x80x9cchip-scalexe2x80x9d package, wherein the package itself, including the die, is of substantially the same dimensions as, or only slightly larger than, the die itself.
The packaging method of the present invention may be applied, by way of example and not limitation, to a die mounted to a leadframe (having a die mounting paddle or in a paddle-less leads-over-chip (LOC), or in a leads-under-chip (LUC) configuration), mounted to a carrier substrate in a chip-on-board (COB) or board-on-chip (BOC) arrangement, a semiconductor die in a so-called xe2x80x9cflip-chipxe2x80x9d configuration, or in other packaging designs, as desired.
The present invention employs computer-controlled, 3-D CAD initiated, stereolithographic techniques to apply protective and alignment structures to an electronic component such as a semiconductor die. A dielectric layer or layer segments may be formed over or adjacent a single die or substantially simultaneously over or adjacent a large number of dice or die locations on a semiconductor wafer or other large-scale semiconductor substrate, individual dice or groups of dice then being singulated therefrom. The package may be formed to cover the lateral surfaces as well as the upper and/or lower surfaces of a semiconductor die.
Precise mechanical alignment of singulated semiconductor dice or larger semiconductor substrates having multiple die locations is not required to practice the method of the present invention, which includes the use of machine vision to locate dice and features or other components thereon or associated therewith (such as leadframes, bond wires, solder bumps, etc.) or features on a larger substrate for alignment and material disposition purposes.
In one embodiment, packaging for electronic components according to the invention is fabricated using precisely focused coherent electromagnetic radiation in the form of an ultraviolet (UV) wavelength laser under control of a computer and responsive to input from a machine vision system such as a pattern recognition system to fix or cure a liquid material in the form of a photopolymer.
A multilayer package structure is formed by placing an object in a bath of photopolymer material to a depth forming a thin liquid layer which will comprise the lowermost layer of the package structure. A laser beam of coherent radiation is controllably passed over selected portions of the thin layer of photopolymer material for partial polymerization thereof. The object is then lowered to a depth to form a second thin liquid layer of photopolymer material over the at least partially polymerized prior layer, followed by laser exposure. A stack of at least partially polymerized layers is thus formed, comprising as many consecutive, at least partially superimposed layers as are required to achieve the desired structure height.
In the structure fabrication process, small interstitial horizontal crevices are defined at the joints between adjacent layers of the structure. Unpolymerized liquid photopolymer material forms a meniscus in each of the crevices. As such uncured material is typically rinsed from the structure after it is removed from the bath, a subsequent complete cure of the photopolymer of the structure outside of the bath does not fill the crevices, but leaves such crevices as unsightly, rough surface features which reduce the effective wall thickness of the structure and may also undesirably collect dust, dirt and moisture.
The present invention includes methods and apparatus for substantially eliminating these interlayer crevices and smoothing the joints between the structure layers. Following the exemplary formation of a desired multilayer package structure about an object such as a semiconductor die, the die with surrounding package structure is removed from the photopolymer bath and excess liquid photopolymer drained therefrom. The object is then tilted by about 5-90 degrees from the horizontal so as to reorient the side walls thereof to face at least partially upwardly, and the crevices between horizontal at least partially cured photopolymer layers, each containing a meniscus of unpolymerized liquid photopolymer, are subjected to radiation of an appropriate wavelength to polymerize the liquid meniscus material and smooth the exterior surfaces of the package structure.
It is also contemplated that the present invention has utility with respect to the formation of stand-alone structures and not merely structures fabricated in association with pre-existing objects, such as the aforementioned semiconductor dice or other electronic components.